Master SystemVerilog, Universal Verification Methodology, and real-world SoC verification through interactive digital books with live Verilator simulation, multi-file code editors, and complete course curricula.
Comprehensive SystemVerilog course covering data types, arrays, OOP, constraints, functional coverage, assertions, IPC, and processes. Original content from mbits-mirafra.
Deep dive into UVM methodology — base classes, reporting, factory, phases, TLM, sequences, configuration database, and complete testbench architecture with live simulation.
Complete digital book covering all 14 modules: UVM core utilities, Wishbone VIP, config regex, RAL register layer, reactive sequences, DMA coverage closure, and multi-subsystem OpenRISC SoC.
Official IEEE 1800.2 edition: 12 comprehensive modules, all 109 textbook listing pointers (Listing 4.1 to 22.4), migration guides from UVM 1.2, and full SoC interconnect testbenches with live simulation.
The SystemVerilog Course (19 Modules, 41 Labs) and UVM Methodology Course (10 Modules, 28 Labs) curriculum, problem statements, and reference verification testbenches are authored by Mbits Mirafra (github.com/mbits-mirafra). Their dedication to educating VLSI and digital design verification engineers has made high-quality open-source learning accessible worldwide.