🏆 Mbits Mirafra Verified Curriculum ⚙️ Dual-Engine Simulation 🌊 Surfer Waveform WASM 55 Modules • 190+ Interactive Labs

Backend Simulators Online

Enterprise Hardware Verification Academy

Hands-on, browser-native digital verification tracks authored by Mbits Mirafra (@mbits-mirafra). Compile, simulate, and debug multi-file testbenches with Verilator 5.050 (native C++ binary execution) and Xezim (instant sub-second simulation) with zero local tooling required.

📗 Enter SystemVerilog Track (19 Modules, 41 Labs) 📘 Enter UVM Architect Track (10 Modules, 28 Labs) 🌊 Launch Surfer Sandbox

4 Tracks

Complete Verification Curriculum

55 Modules

SV, UVM, Wishbone & IEEE 1800.2

190+ Labs

Interactive Executable Testbenches

0 Install

Runs 100% in Modern Web Browsers

⚡ Core Master Verification Tracks

Showing 2 Core Tracks • 69 Hands-On Labs

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Foundation to Advanced • 19 Modules • 41 Labs

SystemVerilog Mastery

Complete mastery of IEEE 1800 SystemVerilog. Build scalable testbenches covering OOP polymorphism, interfaces with modports & clocking blocks, constraint random verification (CRV), concurrent assertions (SVA), functional coverage, and interprocess synchronization.

Track Completion 0 / 19 Modules (0%)

Data Types Dynamic Queues & Arrays Classes & Inheritance Polymorphism Random Constraints Concurrent SVA Functional Coverage Mailboxes & Semaphores Interfaces & Clocking

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Industry Standard • 10 Modules • 28 Labs

UVM Verification Architect

Production-grade Universal Verification Methodology. Architect modular UVM testbenches from scratch with base class hierarchies, automated factory registration, standard 9-phase execution flow, bidirectional sequence-driver handshakes, scoped Config DB, and TLM 1.0/2.0 sockets.

Track Completion 0 / 10 Modules (0%)

Base Classes (uvm_object/component) Factory Overrides 9 Phasing Execution Stimulus & Sequences Driver Handshake Config & Resource DB TLM 1.0 & 2.0 Sockets UVM Topology Visualizer Scoreboard & Coverage VIP

🌊 NEW INTEGRATION Zero-Download WebAssembly Waveform Engine

Live Surfer Waveform Viewer in Every Course

Debug signal transitions with our embedded Surfer WebAssembly viewer. Whenever your SystemVerilog or UVM simulation dumps a VCD trace, it loads directly into your browser tab with full signal tree hierarchy, cursor timing measurements, and multi-radix viewers.

🌊 Open Surfer Sandbox ⚡ Try in SV Course

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Surfer WASM

By surfer-project.org

📚 Specialized Industry Editions & Architecture Reference

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Practical UVM: Step by Step

13 in-depth chapters examining industrial Wishbone interconnect architecture and multi-subsystem OpenRISC SoC testbench environments.

Explore 13 Chapters →

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Practical UVM: IEEE Edition

Comprehensive IEEE 1800.2 standard class reference, 109 textbook code listings, and detailed architectural diff analysis vs UVM 1.2.

Explore IEEE Guide →

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Training Master Catalog

Unified directory connecting all 4 interactive courses, 55 verification modules, and 190+ simulation-ready labs in one central dashboard.

View Master Directory →

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CURRICULUM ARCHITECT & AUTHOR Open-Source Hardware Verification Education

Special Acknowledgements to Mbits Mirafra

The comprehensive SystemVerilog Course (19 Modules, 41 Labs) and UVM Methodology Course (10 Modules, 28 Labs) curriculum, pedagogical sequence, problem formulations, and verified SystemVerilog/UVM testbenches are authored by Mbits Mirafra (@mbits-mirafra).

What The Bug has integrated these industry-standard educational materials into an interactive cloud & desktop verification battle station powered by Verilator 5.050, Xezim, and Surfer Waveforms. We extend our deepest gratitude to Mbits Mirafra for empowering the next generation of ASIC & FPGA verification engineers.

🌐 GitHub: @mbits-mirafra 📦 SVCourse Repository 📦 UVMCourse Repository

Integrated into What The Bug Verification Platform