DESIGN RTL
UVM TESTBENCH
// Click "RUN IP SIMULATION" or "COMPILE / LINT" to test OpenTitan SystemVerilog RTL and UVM testbench on Xezim WASM.
SURFER WAVEFORM VIEWER
WebAssembly · In-Browser
Initializing Surfer...
Functional Coverage
97.8%
TARGET MET
Across All OpenTitan CIP Bins
Covergroups
3 Active
tlul_cg, reg_cg, fsm_cg
SVA Concurrent Assertions
14 Passed
0 Violations Detected
Comportable Bus Check
TL-UL 100%
AccessAck & AckData Handshake
Comportable IP Covergroup Breakdown
Sim Time: 340 ns| Covergroup / Check | Metric Description | Coverpoints / Samples | Score |
|---|
SIMULATION RUNTIME
0.249s
In-Browser Open-Source WASM
ELABORATION & COMPILE
0.087s
Structural Syntax + Elab Stage
WASM HEAP FOOTPRINT
18.4 MB
Zero Server Load · In-Memory
SIMULATOR ENGINE
XEZIM WASM OK
SystemVerilog IEEE 1800 + UVM 1.2
Verification Pipeline Stage Execution
| Pipeline Stage | Engine / Check | Details | Status & Latency |
|---|
| Register Name | Offset | Width | Description & Access |
|---|